1. Field of the Invention
This invention relates generally to fabrication of metal lines and interconnects in semiconductor devices, and more particularly to the fabrication of a copper or Gold metal lines and interconnect using electroless deposition.
2. Description of the Prior Art
The present invention relates to electroless plating and more particularly to the electroless plating of Cu and Ni in semiconductor wires and bumps. It also relates to the formation of high-resolution conductive wiring patterns on semiconductor and advanced packaging substrates.
3. Description of the Prior Art
Electroless plating is a method used to deposit a thin film or a layer of some material on a substrate. The principal step is the immersion of the substrate in a plating bath containing ions of the material to be deposited, causing some of these ions to precipitate at the substrate's surface. Unlike electroplating methods, electroless plating does not require an externally applied electric field to facilitate the ion deposition process. The electroless plating may be selective, i.e., the deposition may occur only at locations that exhibit appropriate electrochemical properties. For example, the ions may be deposited mainly on those portions of the substrate that are made of a material identical (or exhibiting affinity) to the material being deposited. Another of many possibilities is that portions of the substrate may be treated or activated with a catalyst to cause the ion deposition to occur at a rapid rate. The material or catalyst present in the selected areas before the deposition is sometimes referred to as "seed material" or "seed layer". The ratio of the deposition rate on the activated regions to the deposition rate at the non-activated regions is referred to as the "plating process selectivity". The deposition rate may also depend on the physical characteristics of the activated areas, e.g., their sizes, aspect ratios, and distances separating them. If the thickness of the material deposited in various locations at the substrate is similar, the plating process is said to be uniform. For many applications, it is crucial that the plating process be uniform, that it exhibit high selectivity, and that the deposited film strongly adheres to the substrate.
One of the ways to increase the adhesion is to subject the plated artifact to an annealing process. The conditions or process parameters such as the temperature, ion concentration in the plating path, and duration of the bath, which provide desirable uniformity, selectivity, and some physical properties of the deposited layer usually fall within certain ranges, the combination of which is called a "technological process window". To insure the repeatability and consistency of the plating process, it is desirable that the process window be as large as possible.
Electroless plating of solid metals from a solution containing metal ions onto a catalytically active surface has been widely used in the printed circuit board industry for production of wiring layers and inter-layer (via) connections. More recently, this body of knowledge has been applied to producing metal interconnect films in the integrated circuit (IC) industry. The electroless plating technique has several advantages over other well known metal deposition techniques such as sputtering and evaporation. One advantage is that the electroless plating process uses materials and capital equipment that are inexpensive compared to the other methods. Another advantage is that the technique deposits films only in selected, catalytically active regions. This property of selective growth allows the user to reduce the number of lithographic patterning and etching steps used to define the regions to be covered by the deposited metal. It also facilitates dense patterning of materials such as copper, that are difficult to etch anisotropically. Yet another advantage is that the growth rate of the deposited metal is relatively independent of the angles or relative heights of topographic features on the substrate being plated. This property enables deposition into features having high aspect ratios, such as deep via holes on multi-layer circuit boards, that could not be uniformly covered by the "line of sight" deposition techniques such as sputtering and evaporation.
The most commonly published use of electroless plating in the integrated circuit industry is for filling contact or via holes. The traditional contact is a hole, patterned and etched in a dielectric film placed on top of a conducting film so that the surface of the conducting film is exposed within the hole. An upper level of conductor, patterned over the contact hole, makes a physical and electrical contact with the lower conductor in the contact region. Electroless plating has been used to grow metal selectively onto the surface of the lower conductor that is exposed in the contact hole. This produces a metallic "plug" which electrically couples the upper conductor to the lower conductor. The "plug" is plated until its top surface substantially coincides with the top surface of the dielectric, and the resulting planarity of the structure prevents problems that might occur in the subsequent processing if topographic variations were present in the vicinity of the contact region.
Although electroless plating-based processes, such as contact-hole filling, offer many advantages to the process designer, the technique has only found limited acceptance within the IC manufacturing community. Although the technique appears to be relatively simple, the chemical reactions occurring at the plated surface can be complex. Some of the factors inhibiting the wider application of electroless plating are the difficulties in controlling the plating process and in obtaining uniform plating thickness on the entire substrate, as well as the sensitivity to contaminants exhibited by the process. Many of these problems are related to the previously known surface activation techniques, i.e., methods used to render the plated surface catalytically active. The present invention teaches a new surface preparation technique that provides a more active surface on which to plate, thereby improving the latitude of the plating process and the uniformity of the plated materials.
Many surface activation techniques have been reported in both the patent and scientific literature. Frequently, these techniques are designed for plating a specific material onto a specific substrate material, and rely on certain properties of these materials. The most common applications of electroless plating to integrated circuit manufacturing comprise plating of nickel, cobalt, palladium, or copper onto one of two types of substrate surfaces. The first type of substrate surface comprises conductive regions of substrates that are generally formed of silicon, aluminum, or aluminum alloys. The second type of substrate comprises a non-conductor such as silicon dioxide or a polymeric insulator. The reported surface activation techniques applied to these substrates usually fall into one of three categories: (1) catalyst film deposition by evaporation or sputtering, (2) catalyst film deposition by electrochemical surface modification, and (3) catalytic film deposition from a colloidal suspension.
Palladium and platinum are frequently used as catalytic surface activators in electroless plating methods. Catalytic films of palladium or platinum for subsequent electroless plating can be readily deposited by evaporation or sputtering techniques. The films deposited with these techniques can be patterned by well known lithographic techniques, e.g., subtractive etching or liftoff. Large features and/or dense patterns of small features are relatively easy to plate with this method.
It has been reported that the catalytic activity of palladium films deposited by evaporation and sputtering is lower than that of palladium films deposited by other techniques, for example electrochemically deposited films. This low activity has a significant detrimental impact on the uniformity of structures formed by this process and on the resulting yield. Features that are small or separated with large distances from other features are significantly more difficult to plate. These size-dependent and proximity-dependent effects are often related to the presence of stabilizing agents (stabilizers) in the plating solutions. Stabilizers are added to most commercially available plating solutions to prevent the spontaneous decomposition of the plating bath. Generally, the stabilizers reduce or even prevent the auto-catalytic plating reaction from occurring on small particles that may be present in the bath. The presence of such particles may result from a contamination of the plating bath with the airborne dust. The stabilizing agents also exert a significant and beneficial impact on the electrical and mechanical properties of the deposited film, although the mechanisms for this action are not always clearly understood. It is intuitively clear, however, that any mechanism that prevents undesirable auto-catalytic plating on small particles in the bath may also impede the desirable plating of small, isolated features present on the substrate. Plating of small features may be enhanced by modifying the bath composition or process conditions. For instance, the ability to plate sub-micrometer features can be improved by raising the plating bath temperature, or by reducing the amount of the stabilizing agents in the bath. This improvement is obtained at the price of a reduced plating selectivity and reduced bath stability.
The plating non-uniformity and process selectivity also depend on the detailed history of the catalytic surface. Subjecting this surface to any post-patterning clean-up processes or exposing it to air before plating reduce the ability to uniformity plate the desired features.
A wide range of electrochemical surface modification techniques to enable the catalytic plating on metallic and dielectric materials have been disclosed. Aluminum films used in VLSI circuits can be rendered catalytically active by electroless plating of a seed layer of palladium from a bath containing a dilute aqueous solution of PdCl.sub.2 and HCl. Typically, the pre-existing aluminum oxide is removed by a short immersion in a dilute HF solution prior to the palladium activation. The degree of activation achieved by this technique depends strongly on the processing history of the aluminum surface, the concentration of the activator components, the temperature, and duration of the exposure of the aluminum surface of the activator. This method can achieve very high levels of activation, but suffers from a very small "process window". If the exposure to the activator solution is too brief, the insufficient surface activation and the resulting plating non-uniformity will occur. If the exposure to the activator solution is too long, the plated metal will exhibit poor adhesion. While this process has been demonstrated to work, the development of a stable, reproducible manufacturing implementation is difficult.
Another method of activating aluminum surfaces using the electroless deposition of zinc. The zinc is then used as a catalytic seed material for subsequent plating of the nickel film. This process is commonly refereed to as "zincating", and is extremely effective for activating larger dimension patterns but suffers from a reduced process window in the presence of features with small dimensions, such as used in many integrated circuits. The process exhibits a tradeoff between activation and adhesion similar to the one discussed above for palladium-based activation.
Conventionally, the conductor lines are formed by photolithography and dry etching of dielectric and metal layers. However, the Al--Si (or Al--Si--Cu) system does not satisfy many requirements, such as high thermal stability, low electromigration, and high corrosion resistance. Copper is a candidate for multilevel interconnection because of several properties that give it the potential advantages over Al. Unfortunately, copper is quite mobile in Si at elevated temperature and its presence in Si creates trap levels that are deleterious to device operation. For these reasons, it is necessary to determine which materials may act as effective diffusion barrier for copper migration. A suitable diffusion barrier should meet certain constrains:
a. slow transport rate of the substrate and the adjoining material across the barrier layer; PA1 b. slow loss rate of barrier layer into the substrate and adjoining layer; PA1 c. strong adhesion of barrier layer with substrate and with adjoining material; PA1 d. the barrier layer should be laterally uniform in thickness and substrate; PA1 e. the barrier layer should be thermodynamically stable against substrate and adjoining material; PA1 f the barrier layer should have low resistivity. PA1 A contact hole 24 is formed in an insulating layer 20 exposing a substrate 10. The contact hole is defined by sidewalls of the insulating layer. PA1 An adhesion layer 28 is formed on the sidewalls of the insulating layer 20 and the exposed substrate 10. The adhesion layer is preferably composed of Al, Al alloys, Ni, Palladium silicide (PdSi.sub.x), titanium, polysilicon, or amorphous silicon. PA1 A first barrier layer 34 is electrolessly deposited on the adhesion layer 28. The first barrier layer is composed of Ni, Pd, Co, or alloys of Ni, Pd, and Co. PA1 A first metal 38 is selectively electrolessly plated over the first barrier layer 34 filling the contact hole 24. The first metal deposited using an electroless plating process. PA1 A second insulating layer 42 is formed over the first insulating layer. PA1 A second barrier layer 46 is formed over the first metal 38 and the second barrier layer 46. The second barrier layer 46 composed of Ni, Pd or Co. PA1 A second metal layer is selectively electroless plated over the first metal layer filling the via hole 44. The second metal is comprised of Au or Cu.
Electroless copper deposition technique is especially appealing because of low cost and low process temperature, high deposition rate and high quality of electroless Cu deposit. Electroless copper process can be described by two steps which occur simultaneously on the catalytic surface: 1) anodic oxidation of reducing agents and 2) cathodic reduction of metal ions. A catalytic layer is needed for electroless copper deposition to catalyze oxidation of reducing agents and to transport electrons from anodic sites of reaction to cathodic sites of reaction. Hence we must deposit another adhesion layer on the diffusion barrier layer because the surface of diffusion barrier is not autocatalytic.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,674,787(Zhao) Selective electroless copper deposited interconnect plugs for ULSI applications--shows a method utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. A SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer. The SiN or SiON sidewalls, the bottom barrier layer and the cap barrier layer function to fully encapsulate the copper plug in the via.
U.S. Pat. No. 5,308,796(Feldman ) shows a electroless Cu dep using Palladium silicide as a catalytic surface.
U.S. Pat. No. 5,169,680(Ting) shows an electroless deposition of Cu for a metallization.
U.S. Pat. No. 5,183,795(Ting) shows selective electroless deposition of Cu into an interconnect.
U.S. Pat. No. 5,562,760(Ballard et al.), U.S. Pat. No. 4,265,943(Goldstien), discuss electroless metal deposition processes.
Ting, et al., Selective Electroless metal Deposition for Via hole filling in VLSI multi-level Interconnection Structures, J. Electochem Soc. Vol 136, No. 2, Feb. 2, 1989. p. 462 to 466 discuss electroless deposition techniques.
Lopatin et al., Selective Electroless CoWP Deposition onto Pd-activated In-laid Cu lines, Jun. 10-12, 1997 VMIC Conference (1997 ISMIC--107/97/0219 .COPYRGT. p. 219 to 224), discusses electroless deposition techniques.